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www.irf.com 1 3-phase bridge driver product summary description packages the irs213(0, 03, 2)d are hi gh voltage, high speed power mosfet and igbt drivers with three independent high and low side referenced output channels. proprietary hvic technology enables ruggedized monolithic construction. logic inputs are compatible with cmos or lsttl outputs, down to 2.5 v logic. a ground-referenced operational amplifier provides analog feedback of bridge current via an external current s ense resistor. a current trip function which terminates all six outputs is also derived from this resistor. an open drain fault signal indicates if an over-current or undervoltage shutdown has occurred. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use at high frequencies. the floating channels can be used to drive n-channel power mosfets or igbts in the high side c onfiguration which operates up to 600 v. features ? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transi ent voltage, dv/dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for all channels ? over-current shutdown turns off all six drivers ? three independent half-bridge drivers ? matched propagation delay for all channels ? 2.5 v logic compatible ? outputs out of phase with inputs ? cross-conduction prevention logic ? all parts are lead-free ? integrated bootstrap diode function preliminary data sheet no. pd60256 reva irs2130d/irs21303d/irs2132d v offset 600 v max. i o +/- (min.) 200 ma / 420 ma v out 10 v C 20 v (irs213(0,2)d) 13 v C 20 v (irs21303d) t on/off (typ.) 500 ns deadtime (typ.) 2.0 s (irs2130d) 0.7 s (irs213(2,03)d) 28-lead soic 28-lead pdip 4 4 - le a d plcc w / o 1 2 le a ds typical connection applications: *motor control *air conditioners/ washing machines *general purpose inverters *micro/mini inverter drives downloaded from: http:///
www.irf.com 2 irs2130d/irs21303d/irs2132d (j&s)pbf absolute maximum ratings absolute maximum rati ngs indicate sustained limits beyond which dam age to the device may occur. all voltage parameters are absolute voltages referenced to v so . the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. zener clamps are included between v cc & v so (25 v), v cc & v ss (20v), and v bx & v sx (20 v). symbol definition min. max. units v b1,2,3 high side floating supply voltage -0.3 625 v s1,2,3 high side floating offset voltage v b1,2,3 - 20 v b1,2,3 + 0.3 v ho1,2,3 high side floating output voltage v s1,2,3 - 0.3 v b1,2,3 + 0.3 v cc low side and logic fixed supply voltage -0.3 25 v ss logic ground v cc - 20 v cc + 0.3 v lo1,2,3 low side output voltage -0.3 v cc + 0.3 v in logic input voltage ( hin1,2,3, lin1,2,3 & itrip) v ss -0.3 (v ss + 15) or (v cc + 0.3), whichever is lower v flt fault output voltage v ss -0.3 v cc +0.3 v cao operational amplifier output voltage v ss -0.3 v cc +0.3 v ca- operational amplifie r inverting input voltage v ss -0.3 v cc +0.3 v dv s /dt allowable offset supply voltage transient 50 v/ns (28 lead pdip) 1.5 (28 lead soic) 1.6 p d package power dissipation @ t a +25 c (44 lead plcc) 2.0 w (28 lead pdip) 83 (28 lead soic) 78 r th,ja thermal resistance, junction to ambient (44 lead plcc) 63 c/w t j junction temperature 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 c prelim i nary downloaded from: http:///
www.irf.com 3 irs2130d/irs21303d/irs2132d (j&s)pbf recommended operating conditions the input/output logic timing diagram is shown in fig. 1. for proper operation, the device should be used within the recommended conditions. all voltage parameter s are absolute voltage referenced to v so. the v s offset rating is tested with all supplies biased at a 15 v differential. note 1: logic operational for v s of (v so - 8 v) to (v so + 600 v). logic state held for v s of (v so - 8 v) to (v so C v bs ) . (please refer to the design tip dt97-3 for more details). note 2: the cao pin and all input pins (except ca-) are internally clamped with a 5.2 v zener diode. symbol definition min. max. units irs213(0,2)d v s1,2,3 +10 v b1,2,3 high side floating supply voltage irs21303d v s1,2,3 +13 v s1,2,3 +20 v s1,2,3 high side floating offset voltage note 1 600 v ho1,2,3 high side floating output voltage v s1,2,3 v b1,2,3 irs213(0,2)d 10 v cc low side and logic fixed supply voltage irs21303d 13 20 v ss logic ground -5 5 v lo1,2,3 low side output voltage 0 v cc v in logic input voltage (hin1,2,3, lin1,2,3 & itrip) v ss v ss + 5 v flt fault output voltage v ss v cc v cao operational amplifier output voltage v ss v ss + 5 v ca- operational amplifier inverting input voltage v ss v ss + 5 v t a ambient temperature -40 125 c prelim i nary downloaded from: http:///
www.irf.com 4 irs2130d/irs21303d/irs2132d (j&s)pbf static electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss and t a = 25 c unless otherwise specified. the v in, v th, and i in parameters are referenced to v ss and are applicable to all six logic input leads: hin1,2,3 & lin1,2,3. the v o and i o parameters are referenced to v so1,2,3 and are applicable to the respective output leads: ho1, 2,3 or lo1,2,3. note : please refer to feature description section for integrated bootst rap functionality information. symbol definition min. typ. max. units test conditions v ih logic 0 input voltage (out = lo) 2.2 v il logic 1 input voltage (out = hi) 0.8 v v it,th+ itrip input positive going threshold 400 490 580 mv v oh high level output voltage, v bias - v o 1 v v in = 0 v, io= 20 ma v ol low level output voltage, v o 400 mv v in = 5 v, io= 20 ma i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 30 70 a i qcc quiescent v cc supply current 4 6 ma i in+ logic 1 input bias current (out = hi) 300 400 v in = 0 v i in- logic 0 input bias current (out = lo) 220 300 v in = 5 v i itrip+ high itrip bias current 5 100 a itrip = 5 v i itrip- low itrip bias current 10 na itrip = 0 v irs213(0,2)d 7.5 8.35 9.2 v bsuv+ v bs supply undervoltage positive going threshold irs21303d 11 13 irs213(0,2)d 7.1 7.95 8.8 v bsuv- v bs supply undervoltage negative going threshold irs21303d 9 11 irs213(0,2)d 8.3 9 9.7 v ccuv+ v cc supply undervoltage positive going threshold irs21303d 11 13 irs213(0,2)d 8 8.7 9.4 v ccuv- v cc supply undervoltage negative going threshold irs21303d 9 11 irs213(0,2)d 0.3 v ccuvh hysteresis irs21303d 2 irs213(0,2)d 0.4 v bsuvh hysteresis irs21303d 2 v r on, flt fault low on-resistance 55 75 ? i o+ output high short circuit pulsed current 200 250 v o = 0 v, v in = 0 v pw 10 s i o- output low short circuit pulsed current 420 500 ma v o = 15 v, v in = 5 v pw 10 s r bs integrated bootstrap diode resistance 200 ? v os operational amplifier input offset voltage 10 mv v so = v ca- = 0.2 v i ca- ca- input bias current 50 na v ca- = 2.5 v cmrr operational amplifier common mode rejection ratio tbd 80 v so = v ca- = 0.1 v & 1.1 v psrr operational amplifier power supply rejection ratio tbd 75 db v so = v ca- = 0.2 v v cc = 10 v & 20 v v oh,amp operational amplifier high level output voltage 4.9 5.2 5.4 v v ca- = 0 v, v so =1 v v ol,amp operational amplifier low level output voltage 30 mv v ca- = 1 v, v so =0 v prelim i nary downloaded from: http:///
www.irf.com 5 irs2130d/irs21303d/irs2132d (j&s)pbf static electrical charact eristics - (continued) v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss and t a = 25 c unless otherwise specified. the v in, v th, and i in parameters are referenced to v ss and are applicable to all six logic input leads: hin1,2,3 & lin1,2,3. the v o and i o parameters are referenced to v so1,2,3 and are applicable to the respective output leads: ho1, 2,3 or lo1,2,3. symbol definition min. typ. max. units test conditions i src,amp operational amplifier out put source current 4 7 v ca- = 0 v, v so =1 v v cao = 4 v i snk,amp operational amplifier out put sink current 1 2.1 v ca- = 1 v, v so =0 v v cao = 2 v i o+,amp operational amplifier output high short circuit current 10 v ca- = 0 v, v so =5 v v cao = 0 v i o-,amp operational amplifier output low short circuit current 4 ma v ca- = 5 v, v so =0 v v cao = 5 v dynamic electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss , c l = 1000 pf, t a = 25 c unless otherwise specified. symbol definition min. typ. max. units test conditions t on turn-on propagation delay 400 500 700 t off turn-off propagation delay 400 500 700 t r turn-on rise time 80 125 t f turn-off fall time 35 55 v s1,2,3 = 0 v to 600 v t itrip itrip to output shutdown propagation delay 400 660 920 t bl itrip blanking time 400 t flt itrip to fault indication delay 350 550 870 t flt, in input filter time (all six inputs) 325 t fltclr lin1,2,3 to fault clear time irs213(0,2)d lin1,2,3 & hin1,2,3 to fault clear time irs21303d 5300 8500 13700 irs2130d 1300 2000 3100 dt deadtime irs213(2,03)d 500 700 1100 ns sr+ operational amplifier slew rate (+) 5 10 sr- operational amplifier slew rate (-) 2.4 3.2 v/s 1 v input step note: for high side pwm, hin pulse width must be > 1.5 s. prelim i nary downloaded from: http:///
www.irf.com 6 irs2130d/irs21303d/irs2132d (j&s)pbf fig. 1. input/output timing diagram fig. 2. deadtime waveform definitions fig. 3. input/output switching time waveform definitions prelim i nary downloaded from: http:///
www.irf.com 7 irs2130d/irs21303d/irs2132d (j&s)pbf fig. 4. overcurrent shutdown switching time waveform definitions fig. 5. input filter function fig. 6. diagnostic feedback operational amplifier circuit prelim i nary downloaded from: http:///
www.irf.com 8 irs2130d/irs21303d/irs2132d (j&s)pbf lead definitions symbol description hin1,2,3 logic input for high side gate driver outputs (ho1,2,3), out of phase lin1,2,3 logic input for low side gate driver output (lo1,2,3), out of phase fault indicates over-current or undervoltage lock out (low side) has occurred, negative logic v cc low side and logic fixed supply itrip input for over-current shutdown cao output of current amplifier ca- negative input of current amplifier v ss logic ground v b1,2,3 high side floating supply ho1,2,3 high side ga te drive output v s1,2,3 high side floating supply return lo1,2,3 low side gate drive output v so low side return and positive input of current amplifier lead assignments prelim i nary downloaded from: http:///
www.irf.com 9 irs2130d/irs21303d/irs2132d (j&s)pbf functional block diagram prelim i nary downloaded from: http:///
www.irf.com 10 irs2130d/irs21303d/irs2132d (j&s)pbf functional block diagram prelim i nary downloaded from: http:///
www.irf.com 11 irs2130d/irs21303d/irs2132d (j&s)pbf 1 features description 1.1 integrated bootstrap functionality the irs213(0,03,2)d family embeds an integrated bootstrap fet that allows an alternative drive of the bootstrap supply for a wide range of applications. there is one bootstrap fet for each channel and it is connected between each of the floating supply (v b1 , v b2 , v b3 ) and v cc (see fig. 7). the bootstrap fet of each c hannel follows the state of the respective low side output stage (i.e., bootfet is on when lo is high, it is off when lo is low), unless the v b voltage is higher than approximately 1.1(v cc ). in that case the bootstrap fet stays off until the v b voltage returns below that threshold (see fig. 8). fig. 7. simplified bootfet connection vcc=15v vth~17v lo bootfet on bootfet off bootfet on bootstrap fet state phase voltage fig. 8. state diagram bootstrap fet is suitable for most pwm modulation schemes and can be used either in parallel with the external bootstrap network (diode + resistor) or as a replacement of it. the use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations in the following situations: - when used in non-complementary pwm schemes (typically 6-step modulations) - at a very high pwm duty cycle due to the bootstrap fet equivalent resistance (r bs , see page 4). in these cases, better performances can be achieved by using the irs213(0,03,2) non d version with an external bootstrap network. 2 pcb layout tips 2.1 distance from h to l voltage the irs213(0,03,2)j package lacks some pins (see page 8) in order to maximizing the distance between the high voltage and low voltage pins. its strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device (v b1,2,3 , v s1,2,3 ) side. 2.2 ground plane to minimize noise coupling ground plane must not be placed under or near the high voltage floating side. 2.3 gate drive loops current loops behave like an antenna able to receive and transmit em noise (see fig. 9). in order to reduce em coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector-to- gate parasitic capacitan ce. the parasitic auto- inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. gate resistance v sx ( vs0 ) v bx (v cc ) ho x (lo x ) v ge gate drive loop c gc i gc fig. 9. antenna loops 2.4 supply capacitors supply capacitors must be placed as close as possible to the device pins (v cc and v ss for the ground tied supply, v b and v s for the floating supply) in order to minimize parasitic inductance/resistance. prelim i nary downloaded from: http:///
www.irf.com 12 irs2130d/irs21303d/irs2132d (j&s)pbf 2.5 routing and placement power stage pcb parasitic may generate dangerous voltage transients for the gate driver and the control logic. in particular its recommended to limit phase voltage negative transients. in order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray in ductance. see dt04-4 at www.irf.com for more detai led information. prelim i nary downloaded from: http:///
www.irf.com 13 irs2130d/irs21303d/irs2132d (j&s)pbf figures 10-40 provide information on the experimental performance of the irs2132ds hvic. the line plotted in each figure is generated from actual lab data. a large number of individual samples from multiple wafer lots were tested at three temperatures (-40 oc, 25 oc, and 125 oc) in order to generate the experimental (exp.) curve. the line labeled exp. consist of three data points (one data po int at each of the tested te mperatures) that have been connected together to illustrate the understood trend. the individual data points on the curve were determined by calculating the averaged experim ental value of the parameter (for a given temperature). 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on propagation delay (ns) exp . fig. 10. turn-on propagati on delay vs. temperature 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off propagation delay (ns ) exp . fig. 11. turn-off propagati on delay vs. temperature 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) exp . fig. 12. turn-on rise time vs. temperature fig. 13. turn-off fall time vs. temperature 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) exp . prelim i nary downloaded from: http:///
www.irf.com 14 irs2130d/irs21303d/irs2132d (j&s)pbf fig. 14. dt propagation delay vs . temperature fig. 15. t itrip propagation delay vs. temperature 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip to fault propagation delay (ns) exp . 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( o c) fault low on resistance ( ohm) exp . fig. 16. itrip to fault propagation delay vs. temperature fig.17. fault low on resistance vs. temperature fig. 18. v cc quiescent current vs. temperature fig. 19. v bs quiescent current vs. temperature 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) t itrip propagation delay (ns) exp. 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc quiescent supply current (ma) exp . 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs quiescent supply current (ua) exp . 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) dt propagation delay (ns) exp . prelim i nary downloaded from: http:///
www.irf.com 15 irs2130d/irs21303d/irs2132d (j&s)pbf fig. 20. v ccuv+ threshold vs. temperature fig. 21. v ccuv- threshold vs. temperature 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv+ threshold (v) exp . 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv- threshold (v) exp. 6 7 8 9 10 11 - 5 0- 2 5 0 2 55 07 51 0 01 2 5 temperature ( o c) v bsuv+ threshold (v) exp . 6 7 8 9 10 11 - 5 0- 2 5 0 2 55 07 51 0 01 2 5 temperature ( o c) v bsuv- threshold (v) exp . fig. 22. v bsuv+ threshold vs. temperature fig. 23. v bsuv- threshold vs. temperature 0 250 500 750 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip positive going threshold (mv) ex p. 0 250 500 750 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip negative going threshold (mv) exp . fig. 24. itrip positive goi ng threshold vs. temperature fig. 25. itrip negative going threshold vs. temperature prelim i nary downloaded from: http:///
www.irf.com 16 irs2130d/irs21303d/irs2132d (j&s)pbf 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) output high short circuit pulsed current (ma) exp . 0 150 300 450 600 750 -50 -25 0 25 50 75 100 125 temperature ( o c) output low short circuit current (ma) exp . fig. 26. output high short circuit pulsed current vs. temperature fig. 27. output low short circuit current vs. temperature 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 temperature ( o c) "high" itrip bias current (ua) exp . fig. 28. "high" itrip bi as current vs. temperature 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 temperature ( o c) "low" itrip bias current (na) exp . fig. 29. "low" itrip bias current vs. temperature 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) v oh,amp (v) exp . 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 temperature ( o c) v ol,amp (mv) exp . fig. 30. v oh,amp vs. temperature fig. 31. v ol,amp vs. temperature prelim i nary downloaded from: http:///
www.irf.com 17 irs2130d/irs21303d/irs2132d (j&s)pbf fig. 32. sr+,amp vs. temperature fig. 33. sr-,amp vs. temperature fig. 34. i snk,amp vs. temperature 0 5 10 15 20 -50 -25 0 25 50 75 100 125 temperature ( o c) sr+,amp (v/us) exp . 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) sr-,amp (v/us) exp . fig. 35. i src,amp vs. temperature 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) i snk,amp (ma) exp. 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 temperature ( o c) i src,amp (ma) exp . 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature ( o c) i o-,amp (ma) exp . 0 4 8 12 16 20 -50 -25 0 25 50 75 100 125 temperature ( o c) i o+,amp (ma) exp . fig. 36. i o-,amp vs. temperature fig. 37. i o+,amp vs. temperature prelim i nary downloaded from: http:///
www.irf.com 18 irs2130d/irs21303d/irs2132d (j&s)pbf fig. 38. v os,amp vs. temperature fig. 39. psrr vs. temperature fig. 40. cmrr vs. temperature -10 10 30 50 70 90 -50 -25 0 25 50 75 100 125 temperature ( o c) v os,amp (mv) exp . 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 temperature ( o c) psrr (db) exp. 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 temperature ( o c) cmrr (db) exp . prelim i nary downloaded from: http:///
www.irf.com 19 irs2130d/irs21303d/irs2132d (j&s)pbf case outlines prelim i nary downloaded from: http:///
www.irf.com 20 irs2130d/irs21303d/irs2132d (j&s)pbf case outlines prelim i nary downloaded from: http:///
www.irf.com 21 irs2130d/irs21303d/irs2132d (j&s)pbf carrier tape dimension for 28soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 23.70 24.30 0.933 0.956 d 11.40 11.60 0.448 0.456 e 10.80 11.00 0.425 0.433 f 18.20 18.40 0.716 0.724 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 28soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 30.40 n/a 1.196 g 26.50 29.10 1.04 1.145 h 24.40 26.40 0.96 1.039 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c prelim i nary downloaded from: http:///
www.irf.com 22 irs2130d/irs21303d/irs2132d (j&s)pbf carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c prelim i nary downloaded from: http:///
www.irf.com 23 irs2130d/irs21303d/irs2132d (j&s)pbf worldwide headquarters: 233 kansas street, el segundo, ca 90245 tel: (310) 252-7105 this part has been qualifi ed per industrial level http://www.irf.com data and specifications subjec t to change without notice.5/19/2006 order information 28-lead pdip irs2130dpbf 28-lead pdip irs21303dpbf 28-lead pdip irs2132dpbf 28-lead soic irs2130dspbf 28-lead soic irs21303dspbf 28-lead soic irs2132dspbf 44-lead plcc irs2132djpbf 44-lead plcc irs21303djpbf 44-lead plcc irs2132djpbf 28-lead soic tape & reel irs2130dstrpbf 28-lead soic tape & reel irs21303dstrpbf 28-lead soic tape & reel irs2132dstrpbf 44-lead plcc tape & reel IRS2130DJtrpbf 44-lead plcc tape & reel irs21303djtrpbf 44-lead plcc tape & reel irs2132djtrpbf prelim i nary downloaded from: http:///

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